(a) Field of the Invention
This invention relates to a method of forming a multilayer interconnection for a semiconductor device without causing a disconnection.
(b) Description of the Prior Art
FIG. 1 illustrates an example of the conventional semiconductor device provided with a 2-layer interconnection. Reference numeral 1 denotes a silicon substrate on which a semiconductor element is formed. A first aluminium interconnection 3 is formed on said substrate with a SiO.sub.2 layer 2 interposed therebetween. Then, said first aluminium interconnection 3 is covered with a SiO.sub.2 layer 4. After a hole for connecting interconnections with each other is formed in said SiO.sub.2 layer 4, a second aluminium interconnection 5 is formed thereon. The conventional semiconductor-manufacturing device however is accompanied with the drawbacks that if the mismatching of a mask takes place in selectively etching the hole in the SiO.sub.2 layer, said hole will be displaced from its prescribed position in the first aluminium interconnection 3; a narrow groove 6 resulting from overetching appears at the end portion of the hole of the first aluminium interconnection 3; the second aluminium interconnection 5 tends to be broken at said narrow groove 6; to avoid the disconnection of the interconnection, it is necessary to apply an interconnection wider than the hole in consideration of the mismatching of a mask pattern facing the hole; and the broadening of the interconnection will present difficulties in elevating the integration degree of semiconductor elements.